VLSI CAD – Self Paced

The VLSI CAD Curriculum 2025 is a comprehensive program designed for electronics engineers, VLSI enthusiasts, and aspiring chip designers who want to master the fundamentals and advanced techniques of VLSI design and computer-aided design (CAD). This AICTE-aligned curriculum provides learners with hands-on knowledge of logic synthesis, ASIC placement, routing, timing analysis, wirelength estimation, and iterative design improvement techniques.

Participants will explore computational Boolean algebra, Boolean representation via BDDs and SAT, 2-level and multi-level logic synthesis, multilevel factor extraction, and don’t cares. The course also dives deep into ASIC placement strategies, technology mapping, maze routing, interconnect timing, and logic-level timing models, equipping learners with the skills required to optimize VLSI circuits for performance, area, and power.

Through structured modules, learners will gain practical expertise in timing-driven design, technology-aware synthesis, and analytical placement using quadratic wirelength models. By the end of the program, participants will be able to design, optimize, and analyze ASICs and VLSI circuits using CAD tools, preparing them for careers in semiconductor design, chip development, and electronic system engineering.

Course Curriculum Highlights:

Module 1: Orientation

• Overview of VLSI CAD

• Introduction to ASIC design flow

Module 2: Computational Boolean Algebra

• Boolean algebra fundamentals

• Logic representation and simplification techniques

Module 3: Boolean Representation via BDDs and SAT

• Binary Decision Diagrams (BDDs)

• Boolean Satisfiability (SAT) techniques

Module 4: Logic Synthesis

• 2-level logic synthesis

• Multi-level logic synthesis via algebraic models

• Multilevel factor extraction and don’t cares

Module 5: ASIC Placement

• Placement algorithms and strategies

• Iterative improvement with hill climbing

• Analytical placement using quadratic wirelength models

Module 6: Technology Mapping

• Technology mapping as tree covering

• Integration with logic synthesis

Module 7: ASIC Routing

• Routing fundamentals and techniques

• Maze routing: 2-point nets in 1 layer

Module 8: Timing Analysis

• Logic-level timing: basic assumptions and models

• Interconnect timing and electrical models of wire delay

• Wirelength estimation and timing optimization